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September 2001
AS6WA25616
3.0V to 3.6V 256Kx16 IntelliwattTM low-power CMOS SRAM with one chip enable Features
* AS6WA25616 * IntelliwattTM active power circuitry * Industrial and commercial temperature ranges available * Organization: 262,144 words x 16 bits * 3.0V to 3.6V at 55 ns * Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
* 1.5V data retention * Equal access and cycle times * Easy memory expansion with CS, OE inputs * Smallest footprint packages * ESD protection 2000 volts * Latch-up current 200 mA
- 48-ball FBGA - 400-mil 44-pin TSOP 2
* Low power consumption: STANDBY
- 72 W max at 3.6V
Pin arrangement (top view)
44-pin 400-mil TSOP 2 A4 44 1 A5 A3 A6 43 2 A2 3 A7 42 A1 4 OE 41 A0 5 40 UB CS 6 39 LB I/O16 7 38 I/O1 I/O15 I/O2 8 37 I/O14 I/O3 9 36 I/O13 10 I/O4 35 VCC VSS 11 34 VSS VCC 12 33 13 32 I/O5 I/O12 I/O6 14 31 I/O11 I/O7 15 30 I/O10 I/O8 16 29 I/O9 17 WE 28 NC 18 27 A17 A8 19 26 A16 A9 20 25 A10 A15 A14 24 A11 21 A13 23 A12 22 48-CSP Ball-Grid-Array Package
Logic block diagram
A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1-I/O8 I/O9-I/O16 WE Row Decoder VCC 256K x 16 Array (4,194,304) VSS
I/O buffer
Control circuit Column decoder A5 A9 A10 A11 A14 A15 A16 A17
UB OE LB CS
A B C D E F G H
1 LB I/O9 I/O10 VSS VCC I/O15 I/O16 NC
2 3 OE A0 UB A3 I/O11 A5 I/O12 A17 I/O13 NC I/O14 A14 NC A12 A8 A9
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CS I/O2 I/O4 I/O5 I/O6 WE A11
6 NC I/O1 I/O3 VCC VSS I/O7 I/O8 NC
Selection guide
VCC Range Product AS6WA25616 Min (V) 3.0 Typ2 (V) 3.3 Max (V) 3.6 Speed (ns) 55 Power Dissipation Operating (ICC) Max (mA) 2 Standby (ISB1) Max (A) 20
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Copyright (c)Alliance Semiconductor. All rights reserved.
AS6WA25616
Functional description
The AS6WA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words x 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS) permit easy memory expansion with multiple-bank memory systems. When CS is high, or UB and LB are high, the device enters standby mode: the AS6WA25616 is guaranteed not to exceed 72 W power consumption at 3.6V and 55 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low, and UB and/or LB low. Data on the input pins I/O1-O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/ O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), chip select (CS), UB and LB low, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode. These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1-I/O8, and UB controls the higher bits, I/O9-I/O16. All chip inputs and outputs are CMOS-compatible, and operation is from a single 3.0 to 3.6V supply. Device is available in the JEDEC standard 400-mm, TSOP 2, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter Voltage on VCC relative to VSS Voltage on any I/O pin relative to GND Power dissipation Storage temperature (plastic) Temperature with VCC applied DC output current (low) Device Symbol VtIN VtI/O PD Tstg Tbias IOUT Min -0.5 -0.5 - -65 -55 - 1.0 +150 +125 20 Max VCC + 0.5 Unit V V W
C C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS H L L L WE X X H H OE X X H L LB X H X L H L L L L X H L
Key: X = Don't care, L = Low, H = High.
UB X H X H L L H L L
Supply Current ISB ICC ICC
I/O1-I/O8 I/O9-I/O16 High Z High Z DOUT High Z DOUT DIN High Z High Z High Z DOUT DOUT High Z DIN DIN
Mode Standby (ISB) Output disable (ICC) Read (ICC)
ICC
High Z DIN
Write (ICC)
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AS6WA25616
Recommended operating condition (over the operating range)
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Load Current VCC Operating Supply Current IOH = -2.1mA IOL = 2.1mA Test Conditions VCC = 3.0 - 3.6V VCC = 3.0 - 3.6V VCC = 3.0 - 3.6V VCC = 3.0 - 3.6V GND < VIN < VCC GND < VO < VCC; Outputs High Z CS = VIL, VIN = VIL or VIH, IOUT = 0mA, f=0 CS < 0.2V, VIN < 0.2V or VIN > VCC - 0.2V, f = 1 mS CS VIL, VIN = VIL or VIH, f = fMax CS > VIH or UB = LB > VIH, other inputs = VIL or VIH, f = 0 VCC = 3.6V 2.2 -0.5 -1 -1 Min 2.4 0.4 VCC + 0.5 0.8 +1 +1 2 Max Unit V V V V
A A
mA
ICC1 @ 1 MHz
Average VCC Operating Supply Current at 1 MHz
VCC = 3.6V
5
mA
ICC2
Average VCC Operating Supply Current
VCC = 3.6V
40
mA
ISB
CS Power Down Current; TTL Inputs
VCC = 3.6V
100
A
ISB1
CS > VCC - 0.2V or CS Power Down Current; UB = LB > VCC - 0.2V, CMOS Inputs other inputs = 0V - VCC, f=0
VCC = 3.6V
20
A
Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL)
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CS, WE, OE, LB, UB I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF
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Read cycle (over the operating range)
Parameter Read cycle time Address access time Chip select (CS) access time Output enable (OE) access time Output hold from address change CS low to output in low Z CS high to output in high Z OE low to output in low Z UB/LB access time UB/LB low to low Z UB/LB high to high Z OE high to output in high Z Power up time Power down time
Shaded areas indicate preliminary information.
Symbol tRC tAA tACS tOE tOH tCLZ tCHZ tOLZ tBA tBLZ tBHZ tOHZ tPU tPD
Min 55 - - - 10 10 0 5 - 10 0 0 0 -
Max - 55 55 25 - - 20 - 55 - 20 20 - 55
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes 3 3 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5
Key to switching waveforms
Rising input Falling input Undefined/don't care
Read waveform 1 (address controlled)
tRC Address tOH DOUT Previous data valid tAA Data valid tOH
Read waveform 2 (CS, OE, UB, LB controlled)
tRC Address tAA OE tOLZ CS tLZ LB, UB tBLZ DOUT tBA Data valid tBHZ tACS tOHZ tHZ tOE tOH
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Write cycle (over the operating range).
Parameter Write cycle time Chip select to write end Address setup to write end Address setup time Write pulse width Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end UB/LB low to end of write Symbol tWC tCW tAW tAS tWP tWR tAH tDW tDH tWZ tOW tBW Min 55 40 40 0 35 0 0 25 0 0 5 35 Max - - - - - - - - - 20 - - Unit ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 12 12 Notes
Write waveform 1 (WE controlled)
tWC Address tCW CS tBW LB, UB tAS WE tDW DIN DOUT Data undefined tWZ Data valid tOW High Z tDH tAW tWP tAH tWR
Write waveform 2 (CS controlled)
tWC Address tAS CS tAW tBW LB, UB tWP WE tDW DIN DOUT tCLZ High Z tWZ Data undefined Data valid tOW High Z tDH tCW tAH tWR
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Data retention characteristics (over the operating range)
Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Symbol VDR ICCDR tCDR tR Test conditions VCC = 1.5V CS VCC - 0.1V or UB = LB = > VCC - 0.1V VIN VCC - 0.1V or VIN 0.1V Min 1.5V - 0 tRC Max 10 - - Unit V
A
ns ns
Data retention waveform
Data retention mode VCC VCC tCDR CS VIH VDR VIH VDR 1.5V VCC tR
AC test loads and waveforms
VCC OUTPUT 30 pF R2 INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE R1 VCC OUTPUT 5 pF R2 VCC Typ GND (b) Thevenin equivalent: R1 OUTPUT RTH VTH
ALL INPUT PULSES 90% 10% < 5 ns (c) 90% 10%
(a)
Parameters R1 R2 RTH VTH
Notes
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VCC = 3.6V 1523 1142 476 1.4V
Unit Ohms Ohms Ohms Volts
During VCC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is HIGH for read cycle. CS and OE are LOW for read cycle. Address valid prior to or coincident with CS transition LOW. All read cycle timings are referenced from the last valid address to the first transitioning address. CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. 1.5V data retention applies to commercial and industrial temperature range operations. C = 30pF, except at high Z and low Z parameters, where C = 5pF.
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Typical DC and AC characteristics
Normalized supply current vs. supply voltage 1.4 1.2 Normalized ICC 1.0 0.8 0.6 0.4 0.2 0.0 1.7 2.2 2.7 3.2 3.7 VIN = VCC typ TA = 25 C 1.0 Normalized access time vs. supply voltage 3.0 2.5 Normalized TAA Normalized ISB2 0.75 TA = 25 C 0.5 2.0 1.5 1.0 0.5 0.0 VCC = VCC typ VIN = VCC typ Normalized standby current vs. ambient temperature
0.25 0.0 1.7
-0.5
2.2 2.7 3.2 3.7
-55
Supply voltage (V) Normalized standby current vs. supply voltage 1.4 1.2 Normalized ISB 1.0 0.8 0.6 0.4 0.2 0.0 1 2.8 1.9 Supply voltage (V) 3.7 VIN = VCC typ TA = 25 C ISB2
Supply Voltage (V)
25 105 Ambient temperature (C) Normalized ICC vs. Cycle Time
1.5 VCC = 3.6V TA = 25 C
Normalized ICC
1.0
0.50
0.10 1 5 10 Supply voltage (V) 15
Package diagrams and dimensions
44-pin TSOP 2
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
c
Min (mm) A A1 A2 b c d e He E l 0.05 0.95 0.25 18.28 10.06 11.56 0.40
Max (mm) 1.2 1.05 0.45 18.54 10.26 11.96 0.60
44-pin TSOP 2
e He
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
d l 0-5
0.15 (typical)
A A1 b E
A2
0.80 (typical)
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AS6WA25616
48-ball FBGA Bottom View 6 5 4 3 2 1 Ball #A1 Top View Ball #A1 Index
A B C D E F G H Elastomer A B1 B A C1 SRAM Die C
Side View E2 E E Die E1
Detail View A
D E2 Die 0.3/Typ Y
Minimum A B B1 C C1 D E E1 E2 Y - 6.90 - 10.90 - 0.30 - - 0.22 -
Typical 0.75 7.00 3.75 11 5.25 0.35 - 0.68 0.25 -
Maximum - 7.10 - 11.10 - 0.40 1.20 - 0.27 0.08
Notes 1. Bump counts: 48 (8 row x 6 column). 2. Pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3. Units: millimeters. 4. All tolerance are 0.050 unless otherwise specified. 5. Typ: typical. 6. Y is coplanarity: 0.08 (max).
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Ordering codes
Speed (ns) 55
Ordering Code
AS6WA25616-TC AS6WA25616-BC AS6WA25616-TI AS6WA25616-BI
Package Type
44-pin TSOP 2 48-ball fine pitch BGA 44-pin TSOP 2 48-ball fine pitch BGA
Operating Range Commercial
55
Industrial
Part numbering system
AS6WA SRAM IntelliwattTM prefix 25616 Device number T, B Package: T: TSOP 2 B: CSP/BGA C, I Temperature range: C: Commercial: 0 C to 70 C I: Industrial: -40 C to 85 C
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(c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in lifesupporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

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